Dr. David J. Pearce

Towards Compilation of an Imperative Language for FPGAs

Author(s). Baptiste Pauget, Alex Potanin and David J. Pearce.

Venue. In Workshop on Virtual Machines and Language Implementations (VMIL), pages 47--56, 2018. ©ACM Press

Abstract: Field-Programmable Gate Arrays (FPGA’s) have been around since the early 1980s and have now achieved relatively widespread use. For example, FPGAs are routinely used for high-performance computing, financial applications, seismic modelling, DNA sequence alignment, software defined networking and, occasionally, are even found in smartphones. And yet, despite their success, there still remains something of a gap between programming languages and circuit designs for an FPGA. We consider the compilation of an imperative programming language, Whiley, to VHDL for use on an FPGA. A key challenge lies in splitting an arbitrary function into a series of pipeline stages, as necessary to expose as much task parallelism as possible. To do this, we introduce a language construct which gives the programmer control over how the pipeline is constructed.

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